Gate reflectometry of single-electron box arrays using calibrated low temperature matching networks

Sensitive dispersive readouts of single-electron devices (“gate reflectometry”) rely on one-port radio-frequency (RF) reflectometry to read out the state of the sensor. A standard practice in reflectometry measurements is to design an impedance transformer to match the impedance of the load to the characteristic impedance of the transmission line and thus obtain the best sensitivity and signal-to-noise ratio. This is particularly important for measuring large impedances, typical for dispersive readouts of single-electron devices because even a small mismatch will cause a strong signal degradation. When performing RF measurements, a calibration and error correction of the measurement apparatus must be performed in order to remove errors caused by unavoidable non-idealities of the measurement system. Lack of calibration makes optimizing a matching network difficult and ambiguous, and it also prevents a direct quantitative comparison between measurements taken of different devices or on different systems. We propose and demonstrate a simple straightforward method to design and optimize a pi matching network for readouts of devices with large impedance, \documentclass[12pt]{minimal} \usepackage{amsmath} \usepackage{wasysym} \usepackage{amsfonts} \usepackage{amssymb} \usepackage{amsbsy} \usepackage{mathrsfs} \usepackage{upgreek} \setlength{\oddsidemargin}{-69pt} \begin{document}$$Z \ge 1\hbox {M}\Omega$$\end{document}Z≥1MΩ. It is based on a single low temperature calibrated measurement of an unadjusted network composed of a single L-section followed by a simple calculation to determine a value of the “balancing” capacitor needed to achieve matching conditions for a pi network. We demonstrate that the proposed calibration/error correction technique can be directly applied at low temperature using inexpensive calibration standards. Using proper modeling of the matching networks adjusted for low temperature operation the measurement system can be easily optimized to achieve the best conditions for energy transfer and targeted bandwidth, and can be used for quantitative measurements of the device impedance. In this work we use gate reflectometry to readout the signal generated by arrays of parallel-connected Al-AlOx single-electron boxes. Such arrays can be used as a fast nanoscale voltage sensor for scanning probe applications. We perform measurements of sensitivity and bandwidth for various settings of the matching network connected to arrays and obtain strong agreement with the simulations.


Calibration and Error correction protocol
The systematic errors due to cables, connectors, and all other linear non-idealities of the measurement system can be represented in a circuit model with the introduction of an "error box" (EB), so that the real instrument (in our case, UHF ZI Lockin) is replaced with an ideal instrument and EB. The EB is simply a 2-port network whose behavior encapsulates all the errors of the system, as shown in Figure S1. By performing an error calibration, these non-idealities can be quantified and mathematically removed from subsequent measurements. In doing so, it allows measurements to be compared quantitatively against measurements taken on other systems, or against circuit models. For SOL calibration, as the name implies, the three impedances chosen are Short (Z=0 Ω), Open (Z = ∞ Ω), and a matched Load (Z = Z 0 =50 Ω). Any three different impedances can be used, however these standard values are a good choice as they cover a large area of the impedance space, increasing the accuracy of the calibration, and are easy to fabricate. To perform a calibration, a reflection measurement at the frequency band of interest is taken for each standard. These will be referred to as the measured reflection given by Γ MS , Γ MO , Γ ML , for the Short, Open, and Load, respectively. These values, along with the expected reflection of each standard (Γ S = −1, Γ O = 1, Γ L =0) are used to calculate three of the S-parameters of the error box (e 11 , e 21 e 12 , e 22 ). Once these error parameters are known, it is simple to de-embed the error box from measurements. The errors are removed from the measured reflection using Γ = Γ M − e 11 Γ M e 22 − e 11 e 22 + e 21 e 12 (1) Here Γ M , is the measured reflection of a DUT and Γ is the error corrected reflection. To compute the error-corrected data (ECD) from raw data a simple Matlab script is used to remove the errors from the measured reflection using equation 1. A useful side Figure S1. Error correction protocol. R.P. is the reference plane at which calibration is performed. In our experiments ZI UHF is used as a network analyzer effect of performing these calibrations is that the gain or attenuation of all the components within the signal path need not be known. All of these will be a part of the extracted error terms and will therefore be automatically corrected when performing an error correction. This is helpful since the precise behavior of these components often varies with frequency and is not precisely characterized. An error correction removes the need to precisely characterize each individual component in the signal path, as the error calibration does it all at once as long as the components remain in their linear regimes. A collection of three known terminations are assembled and measured on a printed circuit board identical to the actual board containing MN elements and devices in three successive thermal cycles within 3 days and error corrections are computed (Fig. S2). ( Figure S2b). For the Short a piece of copper braid was placed atop of the input pad of the inductor and soldered to the ground plane. To represent the Open the space for inductor is left empty on the same piece of coplanar waveguide; the DC resistance of Open is in excess of 1 GΩ. For the Load a 49.9 Ω resistor soldered to the PCB trace of coplanar waveguide is installed in place of the inductor with the same chip size while at the other end the resistor is grounded . The four probe low frequency resistance of the Load is measured using a lock-in amplifier and is found to vary by less than 0.1Ω in the range from 300 K to 3.6 K. For both terminators, it is assumed the impedance is purely resistive, and frequency independent within 1 GHz bandwidth 1 . The measured resistance of R Short < 0.02 Ω within the 300 K to 3.6 K temperature range.

Matching network and DUT assembled on a PCB
An example of two SEBA wire-bonded to two MNs on a PCB is presented in Fig. S3 with components of MNs labeled. RF circuit is assembled on a Rogers RO4350B high frequency substrate with a 240 nH and 270 nH Coilcraft 0805CS ceramic core surface mount inductors soldered to a coplanar waveguide (CPW). In the photo a capacitor C IN is soldered next to the inductor L 1 is clearly visible. Bonding wires (in green) are sketched for visibility.

2/8 3 Results of error correction
An example of raw vs ECD measurements is presented in Fig. S4(a, b). Black curves represent raw data, and red dotted lines correspond to ECD in Fig. S4a-c. Note that multiple ripples in magnitude response and monotonic linear slope in phase response are eliminated after error correction which makes it very easy to identify the minimum in Γ suitable for reflectometry measurements.

Simulation of SEBA admittance
To simulate the gate dependent complex admittance Y (V g ) for a SEBA in accordance with the model 2 the respective components C dyn (V g ) and R Sis (V g ) are calculated individually for each SEB for a frequency at which reflectometry measurements are performed (≈ 400 MHz) and then summed together. To account for random offset charges the phase of the Coulomb blockade oscillations in each SEB is set purely random 3 , while gate (C g =3 aF) and junction (C J =50 aF) capacitances are distributed with a standard deviation of 3% and 20% respectively.
The resistance of the junctions is assumed to be inversely proportional to the junction overlap area 4 so that After the admittances of all (N=200) SEBs are summed together the resulting SEBA admittance curve over a span of a V g sweep of 2V is plotted (Fig. S5). Next, the largest peak in admittance with the steepest slope within this V g span was identified and approximated with two vertically offset sinewaves to represent the real and imaginary portion of SEBA admittance in the vicinity of this peak (inset in Fig. S5). This approximation is then used to model the gate dependent admittance of the SEBA for calculations of bandwidth and sensitivity in the vicinity of the working point positioned in the middle of the rising slopes of the Re(V g ) and Im(V g ) peaks. Note that the resulting average capacitance of the SEBA is on the order of 40 aF with the oscillatory part of it on the order of ±6 aF.

Low temperature MN optimization
The purpose of the Π matching network in this target application (Fig. S6) is to tweak the value of C IN to achieve a close match, i.e. to convert the complex DUT impedance Z DUT ( and thus will boost the magnitude of the parameter of interest, ∆Γ(V g ). In order to match the experimentally observed low temperature characteristics of the MN for varying values of C IN , the Keysight Technologies Advanced Design System (ADS) optimization toolkit is used. As a starting point for modeling, we use the Coilcraft model 5 with scaled down values of DC and skin-effect resistance; the values of C 1 and R 1 (associated with losses in the core) are set as free parameters, and inductance is allowed to change within 5 % of the nominal value. Here we take into account the, experimentally observed by Zirkle 4 , reduction of an inductor's DC resistance is caused by reduction in the resistivity of copper coil, by a factor of ≈ 70 from 300K down to ≈ 10 K and associated reduction of skin-effect resistance proportional to the square root of resistivity ≈ 8 is used as a starting point for optimization. An experiment by Zirkle 4 also revealed very weak temperature dependence of the value of the capacitances C IN (less than 2% for temperature variation from 300K to 3K) used in this work (0805 size surface mount High Q/low ESR ceramic capacitors by Johanson Technology). An  Fig S2. The following parameters are used in simulations L = 247.9 nH , C pad = 467fF (for C 1 = 169.7 fF R DC = .0124 Ohms and K SE = 1.9e − 5 where R SE = K SE * √ F Res ). We also allow for small variations of C pad (≤ 5 fF) based on potential movements of the bond wires between cooling cycles, C IN is tweaked within its tolerance range of 5% ADS hybrid optimization algorithm is used to find an equivalent circuit which best fits the experimental data. The cost function is the difference between |Γ| of the measured response (after calibration) and |Γ| of the simulated response and the fitted model parameters are C 1 , R 1 , and the value of inductance. The optimization is complete when the cost function is below the target of 0.1. The average value of pad capacitance obtained by the optimization is C pad =467 ± 5 fF. Note that the C pad is at least 10 3 times larger than the total capacitance of the SEBA connected in parallel.
The resulting characteristics of MN for the three values of C IN : smaller than (blue) -, close to (green) -, and greater than (red) required for matching are shown in Fig. S7, which confirms a very strong correlation between the experiment and the model. Fig S8 shows a comparison between experimental and simulated data for the magnitude of reflection coefficient |Γ| ( matching conditions must result in minimal reflection) and resonant frequency f Res vs the value of a balancing capacitor C IN . Good correlation between experiment and simulations is observed thus confirming the validity of the used model. Fig. S9 shows a difference between the raw and error-corrected response of the SEBA, ∆ | Γ | (V g ) (a) and phase ∆Θ(V g )(b), respectively to a change in gate voltage V g for the three different values of balancing capacitor C IN . While both raw and error-corrected data are the strongest for a well-matched case (green curves) as a result of applying the CEC protocol the appearance of oscillations in magnitude and phase of reflection coefficient changes very significantly. Namely, it shows that the oscillations in SEBA admittance lead to oscillations in both components of the reflected signal.

Bandwidth and SB magnitude dependence on C IN
To calculate the bandwidth available for the target application (i.e. fast voltage gate sensing with a SEBA) , the RMS magnitude of the sideband generated in response to the small sinusoidal signal gate modulation voltageṼ g at frequency f Mod is computed. The SEBA is modelled as an oscillating complex admittance Y (V g ) composed of its real Re(V g ) and imaginary Im(V g ) parts (see section S4 for details). Modulation signal magnitudeṼ g =3.5 mV RMS is chosen to be small compared to ∆V g =50 mV, the characteristic period of Coulomb oscillations in the SEBA. The working DC bias point (V g ≈ 1.08V ) is shown in Fig. S5. The calculation of sideband magnitude is achieved through a harmonic balance simulation in ADS. This simulation models the SEBA's response to gate modulation after the carrier frequency is set to the MN resonant frequency for each value of C IN 5/8 (Fig. S8b ).
The relative sensitivity of the SEBA is expressed as a ratio, in dB, between the generated single sideband and applied RF carrier voltage for a chosenṼ g of 3.5 mV RMS. To calculate the bandwidth for SEBA sensing ofṼ g , the resulting magnitude of the sideband is graphed versus the modulation frequency. From here the bandwidth is calculated at a -3 dB level below the low frequency portion of the graph (see Fig. 9c in the main text).
We combine calculations of bandwidth and sideband magnitude for a MN composed of L=240 nH, C pad = 467 fF and various settings of C IN , from 0 to 60 pF in the 2D colormap shown in Fig. S10. Note that simulated data underestimate the losses of signal away from the match point (C IN ≈ 32pF) that occur in experiment, in particular near C IN = 0 pF.

Gate reflectometry model comparison
In several recent publications devoted to gate reflectometry 6, 7 the inductor used in the MN is treated as an ideal element with no parasitic components and to account for the experimentally observed losses, revealed by a presence of a dip in the magnitude of reflection coefficient Γ, a leakage resistor to ground parallel to the DUT, R d , is added to a model used by Gonzalez 6 and Ibberson 7 . Below we show that while providing a qualitative guidance, this approach results in significant errors when it comes to quantitative evaluation of sensitivity and bandwidth of the resulting MN.
To illustrate the difference resulting from the two models, A -used in this work and B -used by Gonzalez 6 and Ibberson 7 we perform the following simulations. For model A we use the circuit shown in Fig. S6 with a negligible dielectric loss to ground where inductor L=247 nH with parasitic components experimentally determined at low temperature is connected to a pad with capacitance C pad =467 fF and DUT in parallel with C pad . For model B we use an ideal inductor of the same value connected to a C pad in parallel with the same DUT as in model A, and, following 7 , assume an additional resistive loss to ground parallel to DUT, R d = 30kΩ.
First we calculate matching conditions for both models, and next we evaluate the sensitivity to DUT admittance modulation by calculating a magnitude of the generated side band signal following the method described in section S6.
One immediate consequence of neglecting parasitic parallel capacitance of the inductor in model B (C 1 in Fig. S6 ) is the shift of resonance from ≈ 403 MHz to ≈ 470 MHz assuming the same pad capacitance, C pad . To account for the experimentally observed resonant frequency within model B, the pad capacitance must be unjustifiably increased to C pad = 654 fF. To achieve matching conditions, model A predicts C IN =30 pF, in close correlation with the experiment while model B suggests using a smaller value of C IN =14 pF. In our experiment, a very similar value, C IN =15 pF, was tested and has proven to be too small to achieve a good match (see Fig S7-S9) Next, we compare the predicted sensitivity to gate modulation for both models. For C IN =30 pF model A predicts a bandwidth of 1.2 MHz and a relative sensitivity of -65 dB. By contrast, model B predicts much lower sensitivity, -82 dB, accompanied by a much broader bandwidth (about 6 MHz). The reason for this is fairly straightforward: the addition of unrealistically small shunt resistance R d along with a larger value of C pad reduces the signal from the DUT, and at the expense of sensitivity it widens the bandwidth. Experimental results again confirm the validity of model A.